1. Field of the Invention
The present invention generally relates to fault checking in computer processors, and more specifically, to a computer which has processors associated in pairs, each processor capable of simultaneously multithreading two threads (e.g., a foreground thread and a background thread) and in which the background thread of one processor checks the foreground thread of its associated processor.
2. Description of the Related Art
In a typical superscalar processor, most computing resources are not used every cycle. For example, a cache port may only be used half the time, branch logic may only be used a quarter of the time, etc. Simultaneous multithreading (SMT) is a technique for supporting multiple processing threads in the same processor by sharing resources at a very fine granularity. It is commonly used to more fully utilize processor resources and increase overall throughput.
In SMT, process state registers are replicated, with one set of registers for each thread to be supported. These registers include the program counter, general-purpose registers, condition codes, and various process-related state registers. The bulk of the processor hardware is shared among the processing threads. Instructions from the threads are fetched into shared instruction issue buffers. Then, they are issued and executed, with arbitration for resources taking place when there is a conflict. For example, arbitration would occur if two threads each want to access cache through the same port. This arbitration can be done either in a “fair” method, such as a round-robin method, or the threads can be prioritized, with one thread always getting higher priority over another when there is a conflict.
Dual Processors Checking in Lockstep
Here, two full processors are dedicated to run the same thread and their results are checked. This approach is used in the IBM S/390 G5™. The primary advantage is that all faults, both transient and solid faults, affecting a single processor are covered. A disadvantage is that two complete processors are required for the execution of one thread.
Dual Processors Operating in High Performance/High Reliability Mode
Here, two full processors normally operate as independent processors in the high performance mode. In the high reliability mode, they run the same thread and the results are compared in a manner similar to the previous case. Examples of these are U.S. Patent Application Numbers TBD, and assigned to the present assignee and having app. Ser. Nos. 09/734,117 and 09/791,143, both of which are herein incorporated by reference.
Redundant SMT Approaches Using a Single SMT Processor (AR-SMT and SRT)
Here, the two threads in the same SMT processor execute the same program with some time lag between them. Because the check thread lags in time, it can take advantage of branch prediction and cache prefetching. Consequently, the check thread does not consume all the resources (and time) that the main thread consumes. Consequently, a primary advantage is fault tolerance with less than full hardware duplication and relatively little performance loss. However, a main disadvantage is that solid faults and transient faults of longer than a certain duration (depending on the inter-thread time lag) are not detected because faults of this type may result in correlated errors in the two threads.